Yet another EBAZ4205 writeup#3: PYNQ!

In this post we will leverage our basic Petalinux build to install PYNQ on our EBAZ4205 evaluation board. PYNQ is a framework being developed by Xilinx to interface all of a Zynq boards' capabilities (i.e. custom logic, processing, and peripherals) via a Python environment. It is enabled thanks to the Zynq's unique feature compared to other FPGAs, in which the logic fabric (PL) is actually programmed by the processor (PS) on boot. As a result, running PYNQ enables to use custom logic without the need of an external JTAG programmer.

References:

[1] PYNQ for Cora-Z7-07S and GitHub PYNQ-Cora-Z7-07S. Great walkthrough. I modified it to apply to EBAZ4205 board.
[2] Quick Porting of PYNQ. A general purpose introduction to PYNQ porting. Some useful replies.
[3] Load a PYNQ 2.5 bitstream during power-up. The last nail in the coffin: how to make ethernet work.

Pre-requisites:

• Software tools installed and configured (Ubuntu 18.04.2, Vivado, Petalinux etc. see parts 1, 2). We use 2019.1 installation. This implies PYNQ 2.5.x
• Functional Petalinux boot image. This is not strictly required for the PYNQ build but will make sure that we are working with a properly configured board file.

1. Download and install PYNQ. I used 2.5.4. You can try using other releases but YMMV. Note that 2.5.4 is called image_v2.5.4 while 2.5.1, 2.5 are v2.5.1 and v2.5, respectively (no "image_" addition).

git clone https://github.com/Xilinx/PYNQ.git -b image_v2.5.4

2. Run auto setup script for PYNQ.

source <PYNQ install dir.>/sdbuild/scripts/setup_host.sh 

3. Download and unzip PYNQ rootfs arm v2.5 image (.img). The "official link" leads to the most recent (2.6 at the time of writing):PYNQ - Python productivity for Zynq - Board. To get the 2.5 version go here: PYNQ - Python productivity for Zynq - test, look in google for "PYNQ rootfs v2.5" or get it from Xilinx.

4. Download PYNQ distro .tar, pynq-2.5.tar.gz from  here.

5. Make board directory tree for EBAZ4205

cd ~/PYNQ/boards/

mkdir -p EBAZ4205_PYNQ/petalinux_bsp/meta-user/recipes-bsp/device-tree/files/

6. Make .spec file under the main board directory.

gedit EBAZ4205_PYNQ/EBAZ4205_PYNQ.spec

File content of EBAZ4205_PYNQ.spec:

ARCH_EBAZ4205_PYNQ = arm
BSP_EBAZ4205_PYNQ = EBAZ4205_PYNQ.bsp
STAGE4_PACKAGES_EBAZ4205_PYNQ = pynq ethernet

7. Make system-user.dtsi file:

gedit EBAZ4205_PYNQ/petalinux_bsp/meta-user/recipes-bsp/device-tree/files/system-user.dtsi

File content of system-user.dtsi:

/include/ "system-conf.dtsi"

/ {

model = "EBAZ4205_PYNQ";

compatible = "Custom_PYNQ,EBAZ4205", "xlnx,zynq-7000";

};

&gem0 {

phy-mode = "mii";

phy-handle = <&phy>;

phy: ethernet-phy@0 {

reg = <0>;

};

};

8. Create a .bsp file from petalinux (This is an archived file, don't worry, no need to extract to use).

cd ~/petalinux/2019.1/projects/

source ~/petalinux/2019.1/settings.sh

petalinux-package --bsp -p EBAZ4205_Petalinux_2019_1/ -o EBAZ4205_Petalinux_2019_1

Process should end with "BSP is ready"

9. Copy/move .bsp file to the main board directory. rename it to the board name as defined in PYNQ:

cp EBAZ4205_Petalinux_2019_1.bsp ~/PYNQ/boards/EBAZ4205_PYNQ/EBAZ4205_PYNQ.bsp

The directory tree in the main board folder should look like this:

10. This is the critical part: PYNQ by definition is not loading a bitstream to the FPGA on boot. Therefore the EBAZ4205 ethernet, that is routed through EMIO (and the clock fed into the ethernet controller) will not start unless we specifically make PYNQ load the bitstream to the FPGA. This can be done by disabling the FPGA manager framework and device tree overlay in <PYNQ folder>/sdbuild/makefile (in my case lines 140,141,142 but YMMV):

cd ~/PYNQ/sdbuild/

gedit ~/PYNQ/sdbuild/Makefile

According to this post,  there may be some implication on runtime bitstream loading and device tree overlays. As this does not prevent the use of PYNQ overlays I'm fine with that at the moment, but you might want to look into the references if you need other functionality.

9. Configure paths and source required software environments for the current terminal (from [1]):

export PATH="/opt/crosstool-ng/bin:/opt/qemu/bin:$PATH"

source <path-to-vivado>/Vivado/2019.1/settings64.sh

source <path-to-sdk>/SDK/2019.1/settings64.sh

source <path-to-petalinux>/settings.sh

petalinux-util --webtalk off

10. Be sudo (you can also set your user to password-less sudoer like  here).

sudo echo hello

11. Make PYNQ image from ~/PYNQ/sdbuild (define your path to the .tar and .img files):

cd ~/PYNQ/sdbuild/

make PREBUILT=~/Downloads/bionic.arm.2.5.img PYNQ_SDIST=~/Downloads/pynq-2.5.tar.gz BOARDS=EBAZ4205_PYNQ BOARDDOR=~/PYNQ/boards/

12. The build process takes about an hour. Final image size ~5.4GB. and a /boot and /dist directories are generated with it. If failed for any reason, clean before rebuild.

make clean

13. The result image is at   <PYNQ folder>/sdbuild/output/<board name>-2.5.img. Burn the image on an SD card formatted as FAT32. I verified it with win32diskimager v0.9.5, but you can follow Appendix — Python productivity for Zynq (Pynq) and use whatever OS you like.

14. If all went well, you should be able to connect ethernet and USB to serial, connect power, and test ethernet. Make sure the FPGA done_0 light and PL red LED turn on:

15. You should be able to log in to your Jupiter network server at http://pynq:9090 (if not, connect the board to the serial console and after login look at the ethernet IP address with ifconfig, and type it in your browser). User: "xilinx". Initial password: "xilinx":

16. Happy hacking!